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1 ? fn8109.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x28hc64 64k, 8k x 8 bit 5 volt, byte alterable eeprom features ? 70ns access time ? simple byte and page write ?single 5v supply ? no external high voltages or v pp control circuits ?self-timed ?no erase before write ?no complex programming algorithms ?no overerase problem ? low power cmos ?40ma active current max. ?200a standby current max. ? fast write cycle times ?64-byte page write operation ?byte or page write cycle: 2ms typical ?complete memory rewrite: 0.25 sec. typical ?effective byte write cycle time: 32s typical ? software data protection ? end of write detection ?data polling ?toggle bit ? high reliability ?endurance: 1 million cycles ?data retention: 100 years ? jedec approved byte-wide pin out ? pb-free plus anneal available (rohs compliant) description the x28hc64 is an 8k x 8 eeprom, fabricated with intersil?s proprietary, high performance, floating gate cmos technology. like all intersil programmable non- volatile memories, the x28hc64 is a 5v only device. it features the jedec approved pinout for byte-wide memories, compatible with industry standard rams. the x28hc64 supports a 64-byte page write operation, effectively providing a 32s/byte write cycle, and enabling the entire memory to be typically written in 0.25 seconds. the x28hc64 also features data polling and toggle bit polling, two methods providing early end of write detection. in addition, the x28hc64 includes a user-optional software data protection mode that further enhances intersil?s hardware write protect capability. intersil eeproms are designed and tested for appli- cations requiring extended endurance. inherent data retention is greater than 100 years. pin configurations nc a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we nc a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 x28hc64 plastic dip flat pack cerdip soic a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 8 a 9 a 11 nc oe a 10 ce i/o 7 i/o 6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 lcc plcc a 7 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 3 a 4 a 5 a 6 a 7 a 12 nc v cc nc we a 8 a 9 a 11 oe 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 nc v ss nc i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce a 10 a 12 nc v cc we nc x28hc64 x28hc64 11 i/o 0 10 a 0 14 v ss 9 a 1 8 a 2 7 a 3 6 a 4 5 a 5 2 a 12 28 v cc 12 i/o 1 13 i/o 2 15 i/o 3 4 a 6 3 a 7 1 16 i/o 4 20 ce 22 oe 24 a 9 17 i/o 5 27 we 19 i/o 7 21 a 10 23 a 11 25 a 8 18 i/o 6 26 nc (bottom view) pga nc x28hc64 tsop nc nc nc nc bottom view data sheet june 7, 2006
2 fn8109.1 june 7, 2006 ordering information part number part marking temperature range (c) access time (ns) package pkg. dwg. # x28hc64em-70 x28hc64em-70 -55 to 125 70 32 ld lcc (458 mil) x28hc64j-70* x28hc64j-70 0 to 70 32 ld plcc n32.45x55 x28hc64ji-70* x28hc64ji-70 -40 to 85 32 ld plcc n32.45x55 x28hc64jiz-70* (note) x28hc64ji-70 z -40 to 85 32 ld plcc (pb-free) n32.45x55 x28hc64jz-70* (note) x28hc64j-70 z 0 to 70 32 ld plcc (pb-free) n32.45x55 x28hc64km-70 x28hc64km-70 -55 to 125 28 ld pga g28.550x650a x28hc64p-70 x28hc64p-70 0 to 70 28 ld pdip e28.6 x28hc64pz-70 (note) x28hc64p-70 z 0 to 70 28 ld pdip** (pb-free) e28.6 x28hc64s-70* x28hc64s-70 0 to 70 28 ld soic (300 mil) m28.3 x28hc64si-70* x28hc64si-70 -40 to 85 28 ld soic (300 mil) m28.3 x28hc64sm-70* x28hc64sm-70 -55 to 125 28 ld soic (300 mil) m28.3 x28hc64sz-70 (note) x28hc64s-70 z 0 to 70 28 ld soic (300 mil) (pb-free) m28.3 x28hc64j-90* x28hc64j-90 0 to 70 90 32 ld plcc n32.45x55 x28hc64ji-90* x28hc64ji-90 -40 to 85 32 ld plcc n32.45x55 x28hc64jiz-90* (note) x28hc64ji-90 z -40 to 85 32 ld plcc (pb-free) n32.45x55 x28hc64km-90 x28hc64km-90 -55 to 125 28 ld pga g28.550x650a x28hc64kmb-90 c x28hc64kmb-90 mil-std-883 28 ld pga g28.550x650a x28hc64p-90 x28hc64p-90 0 to 70 28 ld pdip e28.6 x28hc64pi-90 x28hc64pi-90 -40 to 85 28 ld pdip e28.6 x28hc64piz-90 (note) x28hc64pi-90 z -40 to 85 28 ld pdip** (pb-free) e28.6 x28hc64pz-90 (note) x28hc64p-90 z 0 to 70 28 ld pdip** (pb-free) e28.6 x28hc64s-90* x28hc64s-90 0 to 70 28 ld soic (300 mil) m28.3 x28hc64
3 fn8109.1 june 7, 2006 x28hc64d-12 x28hc64d-12 0 to 70 120 28 ld cerdip x28hc64di-12 x28hc64di-12 -40 to 85 28 ld cerdip x28hc64dm-12 x28hc64dm-12 -55 to 125 28 ld cerdip x28hc64dmb-12 c x28hc64dmb-12 mil-std-883 28 ld cerdip x28hc64fm-12 x28hc64fm-12 -55 to 125 28 ld flatpack (440 mil) x28hc64j-12* x28hc64j-12 0 to 70 32 ld plcc n32.45x55 x28hc64ji-12* x28hc64ji-12 -40 to 85 32 ld plcc n32.45x55 x28hc64jiz-12* (note) x28hc64ji-12 z -40 to 85 32 ld plcc (pb-free) n32.45x55 x28hc64jz-12* (note) x28hc64j-12 z 0 to 70 32 ld plcc (pb-free) n32.45x55 x28hc64kmb-12 c x28hc64kmb-12 mil-std-883 28 ld pga g28.550x650a x28hc64p-12 x28hc64p-12 0 to 70 28 ld pdip e28.6 x28hc64pi-12 x28hc64pi-12 -40 to 85 28 ld pdip e28.6 x28hc64piz-12 (note) x28hc64pi-12 z -40 to 85 28 ld pdip** (pb-free) e28.6 x28hc64pz-12 (note) x28hc64p-12 z 0 to 70 28 ld pdip** (pb-free) e28.6 x28hc64s-12* x28hc64s-12 0 to 70 28 ld soic (300 mil) m28.3 x28hc64si-12* x28hc64si-12 -40 to 85 28 ld soic (300 mil) m28.3 x28hc64siz-12* (note) x28hc64si-12 z -40 to 85 28 ld soic (300 mil) (pb-free) m28.3 x28hc64sz-12 (note) x28hc64s-12 z 0 to 70 28 ld soic (300 mil) (pb-free) m28.3 x28hc64dm-15 x28hc64dm-15 -55 to 125 150 28 ld cerdip x28hc64j-15t1 x28hc64j-15 0 to 70 32 ld plcc tape and reel n32.45x55 x28hc64ji-15 x28hc64ji-15 -40 to 85 32 ld plcc n32.45x55 x28hc64jm-15 x28hc64jm-15 -55 to 125 32 ld plcc n32.45x55 x28hc64jz-15* (note) x28hc64j-15 z 0 to 70 32 ld plcc (pb-free) n32.45x55 x28hc64kmb-15 c x28hc64kmb-15 mil-std-883 28 ld pga g28.550x650a x28hc64p-15 x28hc64p-15 0 to 70 28 ld pdip e28.6 x28hc64piz-15 (note) x28hc64pi-15 z -40 to 85 28 ld pdip** (pb-free) e28.6 x28hc64pz-15 (note) x28hc64p-15 z 0 to 70 28 ld pdip** (pb-free) e28.6 x28hc64s-15 x28hc64s-15 0 to 70 28 ld soic (300 mil) m28.3 x28hc64si-15 x28hc64si-15 -40 to 85 28 ld soic (300 mil) m28.3 *add "t1" suffix for tape and reel. **pb-free pdips can be used for through hole wave solder proces sing only. they are not intended fo r use in reflow solder proces sing applications. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number part marking temperature range (c) access time (ns) package pkg. dwg. # x28hc64
4 fn8109.1 june 7, 2006 pin descriptions addresses (a 0 -a 12 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/write operations. when ce is high, power con- sumption is reduced. output enable (oe ) the output enable input contro ls the data output buff- ers and is used to initiate read operations. data in/data out (i/o 0 -i/o 7 ) data is written to or read from the x28hc64 through the i/o pins. write enable (we ) the write enable input contro ls the writing of data to the x28hc64. pin names block diagram symbol description a 0 -a 12 address inputs i/o 0 -i/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground nc no connect x buffers latches and decoder i/o buffers and latches y buffers latches decoder control logic and timing 65,536-bit eeprom array i/o 0 ?i/o 7 data inputs/outputs ce oe v cc v ss a 0 ?a 12 we address inputs and x28hc64
5 fn8109.1 june 7, 2006 device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this tw o line control architecture eliminates bus contention in a system environment. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the x28hc64 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs first. a byte write operation, once initiated, will automati cally continue to comple- tion, typically within 2ms. page write operation the page write feature of the x28hc64 allows the entire memory to be written in 0.25 seconds. page write allows two to sixty-four byte s of data to be consecutively written to the x28hc64 prior to the commencement of the internal programming cycl e. the host can fetch data from another device within the system during a page write operation (change the source address), but the page address (a 6 through a 12 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the in itial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner. each succ essive byte load cycle, started by the we high to low transition, must begin within 100s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100s, the internal automatic program- ming cycle will commence. th ere is no page write win- dow limitation. effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s. write operation status bits the x28hc64 provides the user two write operation status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. figure 1. status bit assignment data polling (i/o 7 ) the x28hc64 features data polling as a method to indicate to the host system that the byte write or page write cycle has completed. data polling allows a sim- ple bit test operation to determine the status of the x28hc64, eliminating additional interrupt inputs or external hardware. during the internal programming cycle, any attempt to read the last byte written will pro- duce the complement of that data on i/o 7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete, i/o 7 will reflect true data. toggle bit (i/o 6 ) the x28hc64 also provides another method for deter- mining when the internal wr ite cycle is complete. dur- ing the internal programming cycle i/o 6 will toggle from high to low and low to high on subsequent attempts to read the device . when the internal cycle is complete the toggling will ce ase and the device will be accessible for additional read or write operations. 5 tb dp 43210 i/o reserved toggle bit data polling x28hc64
6 fn8109.1 june 7, 2006 data polling i/o 7 figure 2. data polling bus sequence figure 3. data polling software flow data polling can effectively re duce the time for writing to the x28hc64. the timing diagram in figure 2 illus- trates the sequence of events on the bus. the soft- ware flow diagram in figu re 3 illustrates one method of implementing the routine. ce oe we i/o 7 x28hc64 ready last write high z v ol v ih a 0 ?a 12 an an an an an an v oh an write data save last data and address read last address io 7 compare? no yes writes complete? no yes ready x28hc64
7 fn8109.1 june 7, 2006 the toggle bit i/o 6 figure 4. toggle bit bus sequence figure 5. toggle bit software flow the toggle bit can eliminate the chore of saving and fetching the last address and data in order to implement data polling. this can be especially helpful in an array comprised of multiple x28hc64 memories that is fre- quently updated. toggle bit po lling can also provide a method for status checking in multiprocessor applica- tions. the timing diagram in figure 4 illustrates the sequence of events on the bus. the software flow dia- gram in figure 5 illustrate s a method for polling the to g g l e b i t . ce oe we x28hc64 last write i/o 6 high z * * v oh v ol ready * beginning and ending state of i/o 6 will vary. compare no yes ok? compare accum with addr n load accum from addr n last write ready yes x28hc64
8 fn8109.1 june 7, 2006 hardware data protection the x28hc64 provides two hardware features that protect nonvolatile data from inadvertent writes. ? default v cc sense?all write functions are inhibited when v cc is 3v typically. ? write inhibit?holding either oe low, we high, or ce high will prevent an in advertent write cycle dur- ing power-up and power-down, maintaining data integrity. software data protection the x28hc64 offers a software controlled data protec- tion feature. the x28hc64 is shipped from intersil with the software data protection not enabled; that is, the device will be in the st andard operating mode. in this mode data should be protected during power-up/- down operations through the use of external circuits. the host would then have open read and write access of the device once v cc was stable. the x28hc64 can be automatically protected during power-up and power-down without the need for exter- nal circuits by employing the software data protection feature. the internal software data protection circuit is enabled after the first write operation utilizing the soft- ware algorithm. this circuit is nonvolatile and will remain set for the life of the device, unless the reset command is issued. once the software protection is enabled, the x28hc64 is also protected from inadvertent and accidental writes in the powered-up state. that is, the software algorithm must be issued prior to writing additional data to the device. software algorithm selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. refer to figure 6 and 7 for the sequence. the three-byte sequence opens the page write window, enabling the host to write from one to sixty-four bytes of data. once the page load cycle has been com- pleted, the device will automa tically be returned to the data protected state. x28hc64
9 fn8109.1 june 7, 2006 software data protection figure 6. timing sequence?byte or page write figure 7. write sequence for software data protection regardless of whether the device has previously been protected or not, once the software data protection algorithm is used, the x 28hc64 will automatically dis- able further writes unless another command is issued to deactivate it. if no further commands are issued the x28hc64 will be write pr otected during power-down and after any subsequent power-up. note: once initiated, the sequ ence of write operations should not be interrupted. ce we (v cc ) write protected v cc 0v data addr aaa 1555 55 0aaa a0 1555 t blc max writes ok byte or page t wc write last write data xx to any write data a0 to address 1555 write data 55 to address 0aaa write data aa to address 1555 after t wc re-enters data protected state byte to last address address optional byte/page load operation byte/page load enabled x28hc64
10 fn8109.1 june 7, 2006 resetting software data protection figure 8. reset software data protection timing sequence figure 9. software sequence to deactivate software data protection in the event the user wants to deactivate the software data protection feature for testing or reprogramming in an eeprom progra mmer, the following six step algo- rithm will reset the internal protection circuit. after t wc , the x28hc64 will be in st andard operat ing mode. note: once initiated, the sequence of write operations should not be interrupted. ce we standard operating mode v cc data addr aaa 1555 55 0aaa 80 1555 t wc aa 1555 55 0aaa 20 1555 write data 55 to address 0aaa write data 55 to address 0aaa write data 80 to address 1555 write data aa address 1555 write data 20 to address 1555 write data aa to address 1555 x28hc64
11 fn8109.1 june 7, 2006 system considerations because the x28hc64 is frequently used in large memory arrays, it is provided with a two-line control architecture for both read and write operations. proper usage can provide the lowest possible power dissipa- tion, and eliminate the possibility of contention where multiple i/o pins share the same bus. to gain the most benefit, it is recommended that ce be decoded from the address bus, and be used as the primary device selection input. both oe and we would then be common among all devices in the array. for a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. because the x28hc64 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause tran- sient current spikes. the magnitude of these spikes is dependent on the output capa citive loading of the i/os. therefore, the larger the array sharing a common bus, the larger the transient spikes. the voltage peaks associated with the current transients can be sup- pressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recom- mended that a 0.1f high frequency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommen ded that a 4.7f electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the pc board traces. normalized i cc (rd) by temperature over frequency normalized i cc (rd) @ 25% over the v cc range and frequency 1.4 1.2 0.8 0.4 0.6 0.2 1.0 01020 - 55c + 25c frequency (mhz) + 125c 5.5 v cc i cc rd normalized (ma) 1.4 1.2 0.8 0.4 0.6 0.2 1.0 01020 frequency (mhz) 4.5 v cc 5.0 v cc 5.5 v cc i cc rd normalized (ma) x28hc64
12 fn8109.1 june 7, 2006 absolute maximum ratings temperature under bias x28hc64 ......................................... -10c to +85c x28hc64i, x28hc64m .................. -65c to +135c storage temperature.......................... -65c to +150c voltage on any pin with respect to v ss ......................................... -1v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10 seconds).................................. 300c comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indi- cated in the operational sections of this specification) is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) notes: (1) typical values are for t a = 25c and nominal supply voltage (2) v il min. and v ih max. are for reference only and are not tested. temperature min. max. commercial 0c +70c industrial -40c +85c military -55c +125c supply voltage limits x28hc64 5v 10% symbol parameter limits unit test conditions min. typ. (1) max. i cc v cc current (active) (ttl inputs) 15 40 ma ce = oe = v il , we = v ih , all i/o?s = open, address inputs = ttl levels @ f = 10 mhz i sb1 v cc current (standby) (ttl inputs) 12mace = v ih , oe = v il all i/o?s = open, other inputs = v ih i sb2 v cc current (standby) (cmos inputs) 100 200 a ce = v cc - 0.3v, oe = gnd, all i/o?s = open, other inputs = v cc - 0.3v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc , ce = v ih v ll (2) input low voltage -1 0.8 v v ih (2) input high voltage 2 v cc + 1 v v ol output low voltage 0.4 v i ol = 5ma v oh output high voltage 2.4 v i oh = -5ma x28hc64
13 fn8109.1 june 7, 2006 endurance and data retention power-up timing capacitance t a = +25c, f = 1mhz, v cc = 5v a.c. conditions of test mode selection note: (3) this parameter is periodically sampled and not 100% tested. equivalent a.c. load circuits symbol table parameter min. max. unit minimum endurance 100,000 cycles data retention 100 years symbol parameter typ. (1) unit t pur (3) power-up to read operation 100 s t puw (3) power-up to write operation 5 ms symbol parameter max. unit test conditions c i/o (3) input/output capacitance 10 pf v i/o = 0v c in (3) input capacitance 6 pf v in = 0v input pulse levels 0v to 3v input rise and fall times 5ns input and output timing levels 1.5v ce oe we mode i/o power l l h read d out active lhl write d in active h x x standby and write inhibit high z standby x l x write inhibit ? ? x x h write inhibit ? ? 5v 1.92k 30pf output 1.37k waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x28hc64
14 fn8109.1 june 7, 2006 a.c. characteristics (over the recommended operating conditions unless otherwise specified.) read cycle limits read cycle note: (4) t lz min., t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. symbol parameter x28hc64-70 x28hc64-90 x28hc64-12 unit -55c to +125c -55c to +125c -55c to +125c min. max. min. max. min. max. t rc read cycle time 70 90 120 ns t ce chip enable access time 70 90 120 ns t aa address access time 70 90 120 ns t oe output enable access time 35 40 50 ns t lz (4) ce low to active output 0 0 0 ns t olz (4) oe low to active output 0 0 0 ns t hz (4) ce high to high z output 30 30 30 ns t ohz (4) oe high to high z output 30 30 30 ns t oh output hold from address change 0 0 0 ns t ce t rc address ce oe we data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z data valid x28hc64
15 fn8109.1 june 7, 2006 write cycle limits we controlled write cycle notes: (5) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. (6) t wph and t dw are periodically sampled and not 100% tested. symbol parameter min. typ. (1) max. unit t wc (5) write cycle time 2 5 ms t as address setup time 0 ns t ah address hold time 50 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 50 ns t oes oe high setup time 0 ns t oeh oe high hold time 0 ns t wp we pulse width 50 ns t wph (6) we high recovery 50 ns t dv (6) data valid 1s t ds data setup 50 ns t dh data hold 0 ns t dw (6) delay to next write 10 s t blc byte load cycle 0.15 100 s address t as t wc t ah t oes t ds t dh t oeh ce we oe data in data out high z t cs t ch t wp t dv data valid x28hc64
16 fn8109.1 june 7, 2006 ce controlled write cycle page write cycle notes: (7) between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. (8) the timings shown above are unique to page write operations. indi vidual byte load operations wi thin the page write must conf orm to either the ce or we controlled write cycle timing. address t as t oeh t wc t ah t oes t cs t ds t dh t ch ce we oe data in data out high z data valid t cw t dv we oe (7) last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce address* (8) i/o *for each successive write within the page write operation, a 6 ?a 12 should be the same or writes to an unknown address could occur. x28hc64
17 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8109.1 june 7, 2006 data polling timing diagram (9) toggle bit timing diagram (9) note: (9) polling operations are by definition read cycl es and are therefore subject to read cycle timings. address a n d in = x d out = x t wc t oeh t oes a n a n ce we oe i/o 7 t dw d out = x ce oe we i/o* 6 t oes t dw t wc t oeh high z * * * i/o 6 beginning and ending state will vary, depending upon actual t wc . x28hc64
x28hc64 printer friendly version 64k, 8k x 8 bit; 5 volt, byte alterable eeprom datasheets, related docs & simulations description key features parametric data related devices ordering information part no. design-in status temp. package msl price us $ x28hc64d-12 active comm 28 ld cerdip n/a 13.06 x28hc64di-12 active ind 28 ld cerdip n/a 13.61 x28hc64dm active mil 28 ld cerdip n/a x28hc64dm-12 active mil 28 ld cerdip n/a 9.24 x28hc64dm-15 active mil 28 ld cerdip n/a 8.84 x28hc64dmb-12 active mil 28 ld cerdip n/a x28hc64em-70 active mil 32 ld lcc n/a x28hc64fm-12 active mil 28 ld flatpack n/a x28hc64j-12 active comm 32 ld plcc 3 3.87 x28hc64j-12t1 active comm 32 ld plcc t+r 3 3.87 x28hc64j-15t1 active comm 32 ld plcc t+r 3 x28hc64j-70 active comm 32 ld plcc 3 5.53 x28hc64j-70t1 active comm 32 ld plcc t+r 3 5.53 x28hc64j-90 active comm 32 ld plcc 3 5.22 x28hc64j-90t1 active comm 32 ld plcc t+r 3 5.22 x28hc64ji-12 active ind 32 ld plcc 3 4.17 x28hc64ji-12t1 active ind 32 ld plcc t+r 3 4.17 x28hc64ji-12t2 active ind 32 ld plcc t+r 3 4.17 x28hc64ji-15 active ind 32 ld plcc 3 5.33 x28hc64ji-70 active ind 32 ld plcc 3 4.72 x28hc64ji-70t1 active ind 32 ld plcc t+r 3 4.72 x28hc64ji-90 active ind 32 ld plcc 3 4.44 x28hc64ji-90t1 active ind 32 ld plcc 3 4.44 x28hc64ji-90t2 active ind 32 ld plcc t+r 3 4.44 x28hc64jiz-12 active ind 32 ld plcc 3 4.17 x28hc64jiz-12t1 active ind 32 ld plcc t+r 3 4.17 x28hc64jiz-70 active ind 32 ld plcc 3 4.72 x28hc64jiz-70t1 active ind 32 ld plcc t+r 3 4.72 x28hc64jiz-90 active ind 32 ld plcc 3 4.44 x28hc64jiz-90t1 active ind 32 ld plcc t+r 3 4.44 x28hc64jm-15 active mil 32 ld plcc 3 x28hc64jz-12 active comm 32 ld plcc 3 3.87 x28hc64jz-12t1 active comm 32 ld plcc t+r 3 3.87
x28hc64jz-15 active comm 32 ld plcc 3 x28hc64jz-15t1 active comm 32 ld plcc t+r 3 x28hc64jz-70 active comm 32 ld plcc 3 5.53 x28hc64jz-70t1 active comm 32 ld plcc t+r 3 5.53 x28hc64km-70 active mil 28 ld pga n/a x28hc64km-90 active mil 28 ld pga n/a x28hc64kmb-12 active mil 28 ld pga n/a x28hc64kmb-15 active mil 28 ld pga n/a 68.79 x28hc64kmb-90 active mil 28 ld pga n/a x28hc64p-12 active comm 28 ld pdip n/a 2.28 x28hc64p-15 active comm 28 ld pdip n/a 4.73 x28hc64p-70 active comm 28 ld pdip n/a 5.76 x28hc64p-90 active comm 28 ld pdip n/a 5.00 x28hc64pi-12 active ind 28 ld pdip n/a 3.52 x28hc64pi-90 active ind 28 ld pdip n/a 5.60 x28hc64piz-12 active ind 28 ld pdip n/a 3.52 x28hc64piz-15 active ind 28 ld pdip n/a 3.50 x28hc64piz-90 active ind 28 ld pdip n/a 5.60 x28hc64pz-12 active comm 28 ld pdip n/a 2.28 x28hc64pz-15 active comm 28 ld pdip n/a 4.73 x28hc64pz-90 active comm 28 ld pdip n/a 5.00 x28hc64s-12 active comm 28 ld soic 5 4.56 x28hc64s-12t1 active comm 28 ld soic t+r 5 4.56 x28hc64s-12t2 active comm 28 ld soic t+r 5 x28hc64s-12t4 active comm 28 ld soic t+r 5 x28hc64s-12t5 active comm 28 ld soic t+r 5 4.56 x28hc64s-15 active comm 28 ld soic 5 x28hc64s-70 active comm 28 ld soic 3 6.06 x28hc64s-70t1 active comm 28 ld soic t+r 3 6.06 x28hc64s-90 active comm 28 ld soic 3 5.39 x28hc64s-90t1 active comm 28 ld soic t+r 3 5.39 x28hc64si-12 active ind 28 ld soic 5 4.89 x28hc64si-12t1 active ind 28 ld soic t+r 5 4.89 x28hc64si-12t2 active ind 28 ld soic t+r 5 4.89 x28hc64si-15 active ind 28 ld soic 5 x28hc64si-70 active ind 28 ld soic 3 6.57 x28hc64si-70t1 active ind 28 ld soic t+r 5 6.57 x28hc64siz-12 active ind 28 ld soic 3 4.89 x28hc64siz-12t1 active ind 28 ld soic t+r 3 4.89 x28hc64siz-70 active ind 28 ld soic 3 6.57 x28hc64sm-70 active mil 28 ld soic 5 x28hc64sm-70t1 active mil 28 ld soic t+r 5 x28hc64sm-70t2 active mil 28 ld soic t+r 5
x28hc64sz-12 active comm 28 ld soic 3 4.56 x28hc64sz-70 active comm 28 ld soic 3 x28hc64w active comm n/a x28hc64pz-70 coming soon comm 28 ld pdip n/a X28HC64J-90C7871 inactive comm 32 ld plcc 3 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the x28hc64 is an 8k x 8 eeprom, fabricated with intersil?s proprietary, high performance, floating gate cmos technology. like all intersil programmable nonvolatile memories, the x28hc64 is a 5v only device. it features the jedec approved pinout for byte-wide memories, compatible with industry standard rams. the x28hc64 supports a 64-byte page write operation, effectively providing a 32s/byte write cycle, and enabling the entire memory to be typically written in 0.25 seconds. the x28hc64 also features data polling and toggle bit polling, two methods providing early end of write detection. in addition, the x28hc64 includes a user-optional software data protection mode that further enhances intersil?s hardware write protect capability. intersil eeproms are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. key f eatures 70ns access time simple byte and page write single 5v supply no external high voltages or v pp control circuits self-timed no erase before write no complex programming algorithms no overerase problem low power cmos 40ma active current max. 200 a standby current max. fast write cycle times 64-byte page write operation byte or page write cycle: 2ms typical complete memory rewrite: 0.25 sec. typical effective byte write cycle time: 32 s typical software data protection end of write detection data polling toggle bit high reliability endurance: 1 million cycles data retention: 100 years jedec approved byte-wide pin out pb-free plus anneal available (rohs compliant) related documentation datasheet(s): 64k, 8k x 8 bit; 5 volt, byte alterable eeprom technical homepage: digital ics parametric data organization 8kx8-bit access time (ns) 70 active current max. (ma) 40 standby current max. ( a) 200
related devices parametric table x28c010 5v, byte alterable e 2 prom x28c512 5v, byte alterable eeprom x28c513 5v, byte alterable eeprom x28hc256 256k, 32k x 8 bit; 5 volt, byte alterable eeprom about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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